1. Field of the Invention
The invention relates to a design structure for memory circuits, and more particularly to a design structure for content addressable memory circuits.
2. Background Description
A content addressable memory (CAM) is a type of associated memory having an individual logic circuit associated with each memory cell or CAM entry. The individual logic circuits of each memory cell allow for simultaneously comparing the contents of each memory cell of the CAM in a single memory cycle. Because the entire contents of the CAM memory can be searched in one memory cycle, such memories may perform fast searches. CAM memory is especially useful for cache memory as a lookup table to point to an information location for information stored in conventional RAM (random access memory) memory.
As noted above, a benefit of a CAM is its ability to search all entries simultaneously. For example, a CAM that has 1 K entries can be searched in one cycle, while a standard memory (SRAM or DRAM) would typically require 1000 cycles to determine if the desired data is present. Unfortunately, this beneficial aspect of a CAM can also cause functional problems. For example, by searching all the memory cells simultaneously, large current demands can result. Such large current demands typically depend on the specific data contents of the CAM with respect to the search data.
FIG. 1 illustrates a related art CAM array 10 comprising multiple memory cells 12. The memory cells 12 are arranged in rows 28 and columns 29 forming an array. The memory cells 12 in a particular row 28 are connected to one another by a match line 14. The match lines 14 of each row 28 are also connected to a hit logic circuit 19. The memory cells 12 in a particular column 29 are connected to one another by search lines 16. The search lines 16 couple the output of the search drivers 18 to the input of the memory cells 12. An output 32 of the hit logic circuit 19 is connected to the input of a priority logic encoder 24. The hit logic circuit 19 also outputs a hit/miss signal 22, and the priority logic encoder 24 also has a hit/adder output 26.
In operation, the search drivers 18 input the search data into the CAM array 10 through the search lines 16. If the memory cell 12 does not contain the target data, the memory cell 12 causes its associated match line 14 to discharge to ground. If the contents of a particular cell 12 match the applied data received, along its search line 16, the memory cell 12 will allow its match line 14 to remain high. Thus, if all the memory cells 12 in a row 28 match the search data received on the search lines 16, the match line 14 of that row 28 remains high indicating a match. Otherwise, the match line 14 is discharged to ground indicating a mismatch or miscompare, in at least one of the cells 12 on the match line 14. At the end of a search cycle, all the discharged match lines 14 are precharged to a high state in preparation for the next search cycle.
For the CAM architecture of FIG. 1, a miscompare on all the memory cells 12 will result in the discharge, and subsequent restore from low to high of all the match lines 14 within the CAM 10. In this case, all of the search lines 16 and all of the match lines 14 will be switched from low to high within one CAM cycle, causing a large current demand on the power supply powering the CAM memory 10. If previous CAM 10 search cycles resulted in mostly successful compares (or simple CAM writes), and the match lines 14 were not switched, then the instantaneous demand for the peak current may result in significant power supply noise (known as di/dt noise1).
Accordingly, large CAM circuits may draw more current than the power supply can deliver and cause the system to malfunction. Therefore, it has become necessary to define a CAM architecture that can reduce current demand.